(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and, more particularly, to a method for the creation of a high Q value spiral inductor by increasing the metal thickness of the inductor.
(2) Description of the Prior Art
Integrated Circuits (IC""s) are typically formed in or on the surface of a semiconductor substrate whereby electrical circuit elements of the individual IC""s are connected internally to the semiconductor surface on which the IC""s are formed. IC""s that are formed in or on the surface of a substrate are mostly active digital processing devices without therefrom however excluding analog processing devices. In addition, discrete passive components can be formed that ate functionally cooperative with active semiconductor devices and that may or may not have been formed using semiconductor devices technology techniques and equipment.
Semiconductor device performance improvements are largely achieved by reducing device dimensions. This trend of device miniaturization has progressed to where modern day devices are created with sub-micron device feature size. While this process has been a continuing trend for active semiconductor devices it has placed increased emphasis on miniaturization of discrete passive components that are required to function with the miniaturized active devices. To accommodate the requirements that are placed on further reductions of the dimensions of discrete passive components, the methods used and the designs of these components can be changed while another path of development has focused on using materials that provide improved performance of the discrete components. With respect to using more promising materials for the creation of discrete components in order to improve component performance, recent trends have focused on replacing conventional aluminum as the conductive medium with copper. As wire widths in integrated circuits continue to shrink, the electrical conductivity of the wiring material itself becomes increasingly more important. Thus, in this regard, aluminum, which has been the material of choice since the integrated circuit art began, is becoming less attractive than other better conductors such as copper, gold and silver. Copper does provide the advantages of improved conductivity and reliability but does as yet provide a challenge where a layer of copper must be etched using conventional methods of photolithography and reactive ion etching (RIE). This is due to the fact that copper does not readily form volatile species during the process of RIE. To circumvent these problems, other methods of creating interconnect lines using copper have been proposed such as depositing the copper patterns using methods of Chemical Vapor Deposition (CVD) of selective electroless plating. The composition of the deposited layer of metal, if the preferred element contained in the layer of metal is copper, can be changed by the addition of other metallic substances in order to improve deposition results. The use of copper has recently found increased application in the creation of discrete components, most notably of discrete inductors that are formed above the surface of a semiconductor substrate. Copper has only recently gained more attention as an interconnect metal. Copper is of relatively low cost and low resistivity. Copper however also has a relatively large diffusion coefficient into surrounding dielectrics such as silicon dioxide and silicon. Copper has the additional disadvantage of being readily oxidized at relatively low temperatures, conventional photoresist processing can therefore not be used for copper because the photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment. Copper from an electrical interconnect may diffuse into the surrounding layer of dielectric (such as a layer of silicon dioxide), causing the dielectric to become conductive while at the same time decreasing the dielectric strength of the silicon dioxide layer. Copper interconnects are therefore typically encapsulated by at least one diffusion barrier layer in order to prevent diffusion into the surrounding silicon dioxide layer. Silicon nitride can serve as a diffusion barrier to copper, but the prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a high dielectric constant compared with silicon dioxide. The high dielectric constant causes an undesired increase in capacitance between the interconnect and the substrate. Copper further has low adhesive strength to various insulating layers, and it is inherently difficult to mask and etch a blanket copper layer into intricate circuit structures. Copper is also more resistant than aluminum to electromigration, a quality that grows in importance as wire widths decrease.
The invention addresses the creation of an inductor on the surface of a semiconductor substrate using damascene processes. The application of the damascene process continues to gain wider attention for this application, most notably in the process of copper metalization due to the difficulty of copper deposition where a damascene plug penetrates deep into very small, sub-half micron, Ultra Large Scale Integrated (ULSI) devices. While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after CMP and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines, since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. Poor copper gap fill together with subsequent problems of etching and planarization are suspected as the root causes for these damages. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
One of the major challenges that must be faced in the creation of discrete passive components (using digital processing procedures and equipment) is that these components are potentially large in size and can therefore not readily be integrated into digital devices that typically have feature sizes approaching the sub-micron range. The main components that offer this challenge are capacitors and inductors, since both these components can be of considerable size.
Inductors can for instance be applied, concurrent with digital processing capabilities, in the field of modern mobile communication that makes use of compact high-frequency equipment. Continued improvements in the performance characteristics of this equipment has been achieved. Further improvements will place continued emphasis on lowering the power consumption of the equipment, on reducing the size of the equipment, on increasing the frequency of the applications and on creating low noise levels. One of the main applications of semiconductor devices in the field of mobile communication is the creation of Radio Frequency (RF) amplifiers. RF amplifiers contain a number of standard components, a major function of a typical RF amplifier is a tuned circuit that contains inductive and capacitive components. Tuned circuits form, dependent on and determined by the values of their inductive and capacitive components, an impedance that is frequency dependent. The tuned circuit typically presents either a high or a low impedance for signals of a certain frequency. The tuned circuit can therefore either reject or pass and further amplify components of an analog signal, based on the frequency of that component. The tuned circuit can in this manner be used as a filter to filter out or remove signals of certain frequencies or to remove noise from a circuit configuration that is aimed at processing analog signals. The tuned circuit can also be used to form a high electrical impedance by using the LC resonance of the circuit and to thereby counteract the effect of parasitic capacitances that are part of a circuit. One of the problems that is encountered when creating an inductor on the surface of a semiconductor substrate is that the self-resonance that is caused by the parasitic capacitance between the (spiral) inductor and the underlying substrate will limit the use of the inductor at high frequencies. As part of the design of such an inductor it is therefore of importance to reduce the capacitive coupling between the created inductor and the underlying substrate.
Typically, inductors that are created on the surface of a substrate are of a spiral shape, the spiral is created in a plane that is parallel with the plane of the surface of the substrate. Conventional methods that are used to create the inductor on the surface of a substrate suffer several limitations. Most high Q inductors form part of a hybrid device configuration or of Monolithic Microwave Integrated Circuits (MMIC""s) or are created as discrete components, the creation of which is not readily integratable into a typical process of Integrated Circuit manufacturing. It is clear that, by combining the creation on one semiconductor monolithic substrate of circuitry that is aimed at both the function of analog data manipulation and analog data storage and the function of digital data manipulation and digital data storage, a number of significant advantages can be achieved. Such advantages include the reduction of manufacturing costs and the reduction of power consumption by the combined functions. The spiral form of the inductor that is created on the surface of a semiconductor substrate however results, due to the physical size of the inductor, in parasitic capacitances between the inductor wiring and the underlying substrate. These parasitic capacitances have a serious negative effect on the functionality of the created LC circuit by sharply reducing the frequency of resonance of the tuned circuit of the application. Parasitic capacitances have a serious negative effect on the functionality of the created LC circuit by sharply reducing the frequency of resonance of the tuned circuit of the application. More seriously, the inductor-generated electromagnetic field will induce eddy currents in the underlying resistive silicon substrate, causing a significant energy loss that results in low Q inductors.
The performance parameter of an inductor is typically indicated is the Quality (Q) factor of the inductor, The quality factor Q of an inductor is defined as Q=Es/El, wherein Es is the energy that is stored in the reactive portion of the component while El is the energy that is lost in the reactive portion of the component. The Q value of an inductor can also be expressed with the equation Q=W0L/R where W0 is the resonant frequency of oscillation of the inductor, L is the inductive value and R is the resistance of the inductor. This equation further indicates that, for a given value of W0, the Q value of the inductor increases as the resistance of the inductor is decreased. The higher the quality of the component, the closet the resistive value of the component approaches zero while the Q factor of the component approaches infinity. The quality factor for components differs from the quality that is associated with filters or resonators. For components, the quality factor serves as a measure of the purity of the reactance (or the susceptance) of the component, which can be degraded due to parasitics. In an actual configuration, there are always some physical resistors that will dissipate power, thereby decreasing the power that can be recovered. The quality factor Q is dimensionless. A Q value of greater than 100 is considered very high for discrete inductors that are mounted on the surface of Printed Circuit Boards. For inductors that form part of an integrated circuit, the Q value is typically in the range between about 3 and 10.
In creating an inductor on a monolithic substrate on which additional semiconductor devices are created, the parasitic capacitances that occur as part of this creation limit to about 10 the quality factor that can be achieved for the inductor using the conventional silicon process. This limitation is, for many applications, not acceptable. Dependent on the frequency at which the LC circuit is designed to resonate, significantly larger values of quality factor, such as for instance 100 or more, must be available. Prior Art has in this been limited to creating values of higher quality factors as separate units, and in integrating these separate units with the surrounding device functions. This negates the advantages that can be obtained when using the monolithic construction of creating both the inductor and the surrounding devices on one and the same semiconductor substrate. The non-monolithic approach also has the disadvantage that additional wiring is required to interconnect the sub-components of the assembly, thereby again introducing additional parasitic capacitances and resistive losses over the interconnecting wiring network. For many of the applications of a RF amplifier, such as portable battery powered applications, power consumption is at a premium and must therefore be as low as possible. By raising the power consumption, the effects of parasitic capacitances and resistive power loss can be partially compensated, but there are limitations to even this approach. These problems take on even greater urgency with the rapid expansion of wireless applications, such as portable telephones and the like. Wireless communications is a rapidly expanding market, where the integration of RF integrated circuits is one of the most important challenges. One of the approaches is to significantly increase the frequency of operation to for instance the range of 10 to 100 GHz. For such high frequencies, the value of the quality factor obtained from silicon-based inductors is significantly degraded. For applications in this frequency range, monolithic inductors have been researched using other than silicon as the base for the creation of the inductors. Such monolithic inductors have for instance been created using sapphire or GaAs as a base. These inductors have a considerably lower parasitic capacitance than their silicon counterparts and therefore provide higher frequencies of resonance of the LC circuit. Where however more complex applications are required, the need still exists to create inductors using silicon as a substrate. For those applications, the approach of using a base material other than silicon has proven to be too cumbersome while for instance GaAs as a medium for the creation of semiconductor devices is as yet a technical challenge that needs to be addressed. It is known that GaAs is a semi-insulating material at high frequencies, reducing the electromagnetic losses that are incurred in the surface of the GaAs substrate, increasing the Q value of the inductor created on the GaAs surface. GaAs RF chips however are expensive, a process that can avoid the use of GaAs RF chips therefore offers the benefit of cost advantage.
A number of different approaches have been used to incorporate inductors into a semiconductor environment without sacrificing device performance due to substrate losses. One of these approaches has been to selective remove (by etching) the silicon underneath the inductor (using methods of micro-machining) thereby removing substrate parasitic effects. Another method has been to use multiple layers of metal (such as aluminum) interconnects or of copper damascene interconnects.
Other approaches have used a high resistivity silicon substrate thereby reducing resistive losses in the silicon substrate. Resistive substrate losses in the surface of the underlying substrate form a dominant factor in determining the Q value of silicon inductors. Further, biased wells have been proposed underneath a spiral conductor, this again aimed at reducing inductive losses in the surface of the substrate. A more complex approach has been to create an active inductive component that simulates the electrical properties of an inductor as it is applied in active circuitry. This latter approach however results in high power consumption by the simulated inductor and in noise performance that is unacceptable for low power, high frequency applications. All of these approaches have as common objectives to enhance the quality (Q) value of the inductor, to increase the frequency of the LC self-resonance thereby increasing the frequency range over which the inductor can be used, and to reduce the surface area that is required for the creation of the inductor.
When the geometric dimensions of the Integrated Circuits are scaled down, the cost per die is decreased while some aspect,s of performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
One of the approaches of increasing the Q value of an inductor is, as previously highlighted, to reduce the resistance of the inductor. The invention provides a method for the reduction of the resistance of an inductor, increasing the Q value of the inductor.
U.S. Pat. No. 6,054,329 (Burghartz et al.) show a Cu inductor with CMP.
U.S. Pat. No. 6,030,877 (Lee et al.) and U.S. Pat. No. 5,801,100 (Lee et al.) show copper inductors formed using plating processes.
U.S. Pat. No. 5,652,173 (Kirn) shows a Cu inductor with CMP.
A principle objective of the invention is to increase the Q value of an inductive component that is created over the surface of a semiconductor substrate.
Another objective of the invention is to increase the Q value of an inductive component that is created over the surface of a semiconductor substrate without requiring the use of additional steps of mask exposures.
In accordance with the objectives of the invention a new method is provided for the creation of an inductive over the surface of a semiconductor substrate. A first layer of metal is created in a layer of dielectric, a second layer of metal is created overlying the first layer of metal. The first layer of metal combined with the second layer of metal form an inductor of increased height, reducing the resistivity of the inductor, increasing the Q value of the inductor. The new method of creating an inductor can be combined with creating contact points that connect to contact points in the active region of the surface of a semiconductor substrate.